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IMEC identifies hot spots in 3-D mixed IC stacks
7/15/2011 |
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Nicolas Mokhoff
IMEC researchers have proven out that its 3-D design tools have the appropriate thermal models for designing next-generation 3-D stacked chips.
The 3-D stack resembles as close as possible to future commercial chips. It consists of IMEC's proprietary logic CMOS IC on top of which a commercial DRAM is stacked using through-silicon vias (TSVs) and micro-bumps.
Heaters were integrated to test the impact of hot spots on DRAM refresh times. And, the chip contains test structures for monitoring thermo-mechanical stress in a 3-D stack, ESD (electro-static discharge) hazards, electrical characteristics of TSVs and micro-bumps, fault models for TSVs, etc. IMEC's 3-D integrated DRAM-on-logic demonstrator showed that a minimum die thickness of 50µm is required to deal with local hot spots on the logic die, which are generated by local power dissipation.
Due to the strongly reduced lateral heat spreading capability of thin die, these hot spots are higher in temperature and more confined if the die thickness is reduced.
The hot spots on the logic die cause local temperature increases in the memory die. This may cause a reduction in retention time of the DRAM devices.
However, IMEC said that its 3-D stacked demonstrator has proven that the DRAM may not be thermally isolated from the logic die since the DRAM die also acts as an effective heat spreader for the logic die. As such the intensity of the hot spot is reduced and thereby the temperature rise in the DRAM device is strongly limited, according to the IMEC researchers.
The results of the various experiments allowed imec researchers to calibrate thermal models which are implemented in 3-D EDA tools. They have proven to be valuable means to design next-generation 3-D stacked ICs. The design of the 3-D chip is realized together with many players in the 3-D integration supply chain.
"This test-chip and our 3-D design tools and thermal models are an important step for the introduction of 3-D technology in DRAM-on-logic for mobile applications," said Luc Van den hove, president and CEO IMEC, said in a statement. He also added that "to boost the performance towards high-end applications, IMEC will set up a cooling research program."
The 3-D thermal work was executed in collaboration with partners Globalfoundries, Intel, Micron, Panasonic, Samsung, TSMC, Fujitsu, Sony, Amkor and Qualcomm.
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